Scher

Procedure

AC Load Line and Power Analysis

Consider the circuit of Figure $1$ using $Vcc=5$ volts, Vee $=-12$ volts, $Rb=47k,Re=1k,$ Rload $=100$ and $Ce=470F.$ Determine the theoretical and $i_{C(sat)},$ and record these in Table $1.$ It is helpful to plot the AC load line for step three. Note that the collector$-$emitter saturation voltage for a Darlington pair cannot be assumed to be $0$ volts, and may be closer to one volt, thus reducing the expecting voltage swing toward the saturation point. It is also worth noting that this amplifier has a direct coupled input $($i$.$e$.,$ no input capacitor is required due to the very small DC base voltage$).$

Build the circuit of Figure $1$ using $Vcc=5$ volts, Vee $=-12$ volts, $Rb=47k,Re=1k,$ Rload $=100$ and $Ce=470F.$ Disconnect the signal source and measure the DC transistor voltages to ensure the circuit is biased correctly. Record $V_{\text{C}\text{E}\text{Q}}$ and $I_{CQ}$ in Table $1($Experimental$).$

Based on the data recorded in Table $1,$ determine the theoretical maximum unclipped load voltage $($compliance$)$ and record it in Table $2.$ Based on this, determine the maximum load power and record it Table $2$ as well. Also determine and record the expected values for the quiescent power dissipation of the transistor $(P_{DQ}),$ the supplied DC current and power, and the resulting efficiency.

Laboratory Manual for Semiconductor Devices: Theory and Application

$14$

Please solve for Vceq and Iq