Section 4.4 High-Speed Digital Interconnects and Signal Integrity 4.4.1 Digital clock and data pulses should ideally consist of rectangular pulses. Actual clock and data pulses, however, resemble pulses having a trapezoi- dal shape with certain rise/falltimes. Depending on the ratio of the rise/ falltime to the one-way transit time of the transmission line, the received voltage may oscillate about the desired value, possibly causing a digital gate at that end to switch falsely to an undesired state and cause errors. Matching the line eliminates this problem because there are no reflections, but matching cannot always be accomplished. In order to investigate this problem, consider a line connecting two CMOS gates. The driver gate is assumed to have zero source resistance (Rs = 0), and the open-circuit voltage is a ramp waveform (simulating the leading edge of the clock/ data pulse) given by Vs(t)=0 for 1