Show how the instructions below would progress through the 5-stage in-order pipeline lwt3,O(t2) sub t0, t5, t 3 and t1,t3,t4 swt5,O(t1) There is NO forwarding. Assume there is a fast register file! Read and Write to the same register can occur in the same clock cycle Assume also the presence of a hazard detection unit in the ID stage as covered in lectures. This is how you will map the pipeline diagram table to your answer: Each instruction in the pipeline stage will be shown by the letter for the pipeline stage followed by the clock cycle. That is, F2 means that in the 2 nd clock cycle, the instruction is in the F stage. X7 means that in the 7 th clock cycle, the instruction is in the X stage. Accordingly, the table representation for the first instruction (Iw), in the code sequence has been done for you Iw t3, O(t2): F1,D2,X3,M4,W5 sub t0, t 5,t3 and t1,t3,t4 swt5,O(t1) Please be very careful in ensuring there are no typos in your submitted answer! NOTE: Do not add whitespace between characters in your answer. Separate F1,D2,X3,M4,W5 format by commas without whitespace (as shown above for sw)