shows a data flow graph (DFG) to build a fully dedicated architecture (FDA). a + b + Z X Figure Q7 (b) Derive the RTL codes for the design d + X (a) From the DFG, obtain the schedule and resource allocation applying as-late-as-possible (ALAP) scheduling. The design must use only one adder and one multiplier. (10 marks) e (c) Draw the functional block diagram of the datapath unit. (5 marks) (7 marks) (d) It is given that the propagation delay of the components are as follows: adder is 30 ns, multiplier is 200 ns and register is 10 ns. Perform the performance analysis by determining the maximum operating frequency and total execution time of your design. (5 marks)