Simple beep sound using Verilog or VHDL with the help of a DAC code from opencores.org on an digital output using FPGA Spartan 6. (Has no integrated DAC) will use software and RC circuit.

Resource Constraints FILE:

net "clk" loc = p123;

# this was inserted based on a Map error message: NET "n_rst" CLOCK_DEDICATED_ROUTE = false;

net "n_rst" LOC = P118; # 4 P7-48 0N0 net "dout" LOC = P120; # 5 P7-46 0N1

https://opencores.org/project/sigma_delta_dac_dual_loop

Analog FPGA Digital Input Analog Output Delta Sigma DAC Analog FPGA Digital Input Analog Output Delta Sigma DAC