simulate a CMOS NOR Basic Cell

Begin by creating a netlist for your SR-Latch. Your latch should have two inputs (S and R) and two outputs (Q and QN). Be sure to also include ground and V_DD. Make each transistor of your latch minimum-sized (use the minimum width and length for each transistor).

Simulate your SR-latch to ensure that it works properly (use a transient analysis)--test setting Q to 1, holding this output value, resetting Q to 0, holding this output value, asserting set and reset at the same time, and holding this output value. I suggest that you create a subcircuit (in Spice, this is .SUBCKT) of your latch.

You then need to modify your code to create a fanout-of-4 (FO4) at each output of your SR-latch--this is one common way to add load to a circuit in order to more accurately measure its performance. To create a FO4 configuration, use two additional, identical copies of your latch as loads. Connect your Q output to both the S and R inputs of one of your load latches and connect your QN output to both the S and R inputs of your other load latch. You will measure the performance of your first latch and just use the other two copies as loads. You must also use a separate DC source for the V_DD of each latch (this will ensure that you only measure the current of the first latch when calculating power and energy performance).

Obtain the following information from the initial FO4 simulation of your SR-latch and include this in your report:

1) (2 pts) Measure and record the rise-time of output Q (from 10% to 90% of V_DD) and propagation delay (from S to Q) for the set operation. Also measure and record the fall-time of output Q (from 90% to 10% of V_DD) and propagation delay (from R to Q) for the reset operation. I recommend using CosmosScope to make these measurements. Obtain a screenshot of the rise-time/fall-time and propagation delay measurements for either your set or reset operation. Remember: Due to prior academic dishonesty in the class, all screenshots must include the full screen showing (1) the plots/graphs of interest, as well as the remainder of the desktop showing (2) the task bar (or application bar) and (3) the computer clock. Screenshots which do not contain all of these details will receive no credit (will not be graded).

2) (2 pts) Measure and record the average current required (the current from the supply voltage, V_DD) during your SR-Latch's (1) hold operation, (2) set operation, and (3) reset operation (again, I recommend using CosmosScope to make these measurements). Calculate the average power dissipated during your SR-Latch's (1) hold operation, (2) set operation, and (3) reset operation. Also calculate the average energy dissipated during your SR-Latch's (2) set operation and (3) reset operation. Obtain a screenshot of the waveform showing your average current measurement for either your set or reset operation. Remember: Due to prior academic dishonesty in the class, all screenshots must include the full screen showing (1) the plots/graphs of interest, as well as the remainder of the desktop showing (2) the task bar (or application bar) and (3) the computer clock. Screenshots which do not contain all of these details will receive no credit (will not be graded).

3) (1 pt) Obtain a screenshot of a waveform of your inputs (S and R) and outputs (Q and QN) showing you first asserting set and reset at the same time, and afterwards, immediately performing the hold operation. Describe what behavior you are observing and why this is occurring. Remember: Due to prior academic dishonesty in the class, all screenshots must include the full screen showing (1) the plots/graphs of interest, as well as the remainder of the desktop showing (2) the task bar (or application bar) and (3) the computer clock. Screenshots which do not contain all of these details will receive no credit (will not be graded).

Now resize your transistors (change the NMOS and/or PMOS widths) to obtain equal rise- and fall-times. Do this in your Spice subcircuit (to ensure that all of your latches (the SR-Latch being measured and the two load latches) are still identical). Now obtain the following information from the FO4 simulation of your resized SR-Latch and include this in your report:

4) (1 pt) List and explain the widths you chose for each of your transistors

• For example: what calculations did you perform, what was the sequence of changes/simulations you performed which led you to your final transistor values, etc.

5) (2 pts) Repeat steps 1 and 2 (from above) for your new, resized SR-Latch

6) (1 pt) Compare and explain these results with your initial, minimum-sized SR-Latch

• For example: how did the delays change (what percent increases/decreases and why?), how did the powers change (what percent increases/decreases and why?), etc.