Solve in verilog code Design a one$-$input, one$-$output serial $2\text{'}$s complementor. The circuit accepts a string of bits from the input and generates the $2\text{'}$s complement at the output. The circuit can be reset asynchronously to start and end the operation.Test your circuit using the following input sequence$\mathrm{.}1)0101111101111002)$ Random sequence of your choice.Show me test code and design code