Question: solve this 6. 6.1) Design a positive edge triggered DFF. No transistor sizes are needed and you may use any logic gate symbols (without showing

solve this

6. 6.1) Design a positive edge triggered DFF. No transistor sizes are needed and you may use any logic gate symbols (without showing their transistor level imple- mentation) in your design. (10) 6.2) Modify your design to add a low-active asynchronous reset function. (5) 6.3) Modify your design to add a low-active clock enable function.

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