solve time 25 minute ...quicly answer

Consider the following code block sw $t1, 4(52) LN $t), 452) 1 Sti, $t2, st1 If you only use Stall and code scheduling to overcome the data hazard in the above code sequence, how many clock cycles are needed? Consider the following duration for each stage IF - 220 ns ID 125 ns EX (addition) - 250 ns EX (shift) - 120 ns EX (subtraction = 220 ns MEM= 150 WB = 175 ms If we consider the above timing, how many stalls would be needed if we want to overcome the data hazard using Stalls and code scheduling? For executing One lw instruction, how much longer will it take to execute the instruction with 5 stage pipelining compared to single cycle datapath? (only write the value, don't need to mention unit)