Squidward has decided to branch out into hardware design. Being new to the field, hes asking for your help in designing a pipeline of a new processor. Once the processor has been built, hes going to test it with a sample program that contains 2x109 instructions.

(c). Assume the current state-of-the-art pipeline has 15 stages. Assume also that the stages are perfectly balanced. How much speedup will it achieve compared to the non-pipelined single cycle processor? Be exact here!

(d). Realistically, we cannot achieve ideal speedup due to the overhead of implementing pipelining stages (e.g. imperfectly balanced stages, adding pipeline registers, etc). Does this overhead affect the instruction latency, instruction throughput, or both? For each metric affected, is the effect significant? Why or why not?