Suppose that you are told that a system with one level of cache has an average memory access time of 3.2 clock cycles. A memory access that results in a cache hit requires one clock cycle, while a memory access that results in a cache miss requires 60 clock cycles. What is the cache miss rate? You are considering adding a second level of cache. This cache is com- pletely independent of the first level. At this level, a memory access that results in a cache hit requires four clock cycles, while a memory access that results in a cache miss requires 60 clock cycles. Considering the two caches together, what is the minimum cache hit rate required for the second cache such that the average access time decreases by a factor of two?