The average memory access time for a microprocessor with 1 level of cache is 3 clock cycles - If data is present and valid in the cache, it can be found in 1 clock cycle - If data is not found in the cache, 60 clock cycles are needed to get it from off-chip memory Designers are trying to improve the average memory access time to obtain a 50% improvement in average memory access time, and are considering adding a 2 nd level of cache on-chip. Assuming that that second level of cache could be accessed in 6 clock cycles, and this change does not affect the first level cache's access patterns or hit times, and off chip accesses would still require 60 clock cycles. To obtain the desired speedup, how often must data be found in the 2 nd level cache?