Suppose we have 10,000 lines in our program and our computer system has four pipeline stages. How many cycles would it take to run the entire program if there were no stalls? (Ideal pipeline) Now, suppose our 10,000 line program has following characteristics: 5% of instructions are memory writes, and the cache hit rate is 90%. Reading contiguous data from one single memory location takes 12 clock cycles (no matter the size of data read). Writing contiguous data to main memory takes 10 clock cycles (no matter the size of data written). Reading from and writing to main memory cannot take place simultaneously. Assume that the cache block size is 8 words. How many additional cycles would be caused by memory write instructions if write back and write-allocate policy is implemented? Assume that when a cache entry needs to be replaced, 40% of the time the dirty bit is 1. How many additional cycles are caused by memory writes if write-through and no write-allocate policy is implemented