Suppose we have a $2-$way set associative cache for instructions.$$ All instructions are $4$ bytes $($e$.$g$.,$ MIPS architecture$).$ The cache can store $8$ instructions, or $32$ bytes.$$ Suppose the cache is initially empty and then the following loop is run:

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Address $($decimal$)$

Instructions

Comments

$0$

LOAD A$,100$

Register A $=100$

$1$

Call$10$

Subroutine call to Address $10$

$2$

DEC A

Decrements A by $1,$ i$.$e$.,$ A $=$A$-1$

$3$

JANZ$1$

Jump to address $1$ if A $0$

$4$

STOP

Stop the program

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$10$

INC B

Increment register B by $1,$ i$.$e$.,$ B $=$ B$+1$

$11$

RET

Return from subroutine

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$($a$)[1$ pt$]$ If the cache is direct mapped, how many misses will there be$?$

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$($b$)[1$ pt$]$ If the cache were $2-$way set associative, how many misses will there be$?$