Suppose we have a system with $8-$byte words and a cache with $32-$byte blocks connected directly to memory. The cache has a hit time of $15$ ns$.$ The bus to memory is $8$ bytes wide, requesting a word from memory takes $90$ ns $($total$,$ aka round trip time$),$ and memory bus transactions are serialized $($not pipelined$).$ The baseline cache requests each word from memory sequentially on a miss, and waits to respond to the CPU until miss repair is fully complete. Consider a workload with poor locality, with a cache hit rate of only $15\%.$ Show your work.

$($a$)$ What is the AAT speedup of early restart over baseline? Assume a uniform distribution of accesses to each word in a block $(25\%$ chance of each$).$ This means that $25\%$ of misses are for word $1$ in a block, $25\%$ for word $2,25\%$ for word $3,$ and $25\%$ for word $4.($b$)$ What is the AAT speedup over baseline of early restart if the distribution of accesses to each word in a block is $10\%,10\%,55\%,$ and $25\%,$ respectively?

$($c$)$ What is the AAT speedup over baseline with critical word first with early restart?