Suppose we have a system with $8-$byte words and a cache with $32-$byte blocks connected directly to memory. The cache has a hit time of $15$ ns$.$ The bus to memory is $8$ bytes wide, requesting a word from memory takes $90$ ns $($total$,$ aka round trip time$),$ and memory bus transactions are serialized $($not pipelined$).$ The baseline cache requests each word from memory sequentially on a miss, and waits to respond to the CPU until miss repair is fully complete. Consider a workload with poor locality, with a cache hit rate of only $15\%.$