Suppose we want to execute the following code segment on the pipelined CPU: add $2, $5, $4 add $4, $2, $5 lw $5 100 ($2) add $3, $2, $5 Suppose there is no hardware supports for the forwarding and the stalling, but the register file can be written at the first half of cycle and be read at the second half How many NOPs and at what places that you can add to make the code segment execute correctly on our pipeline? Suppose the pipeline stalls, but no forwards, when there is data hazard. How many cycles will the above code segment execute