Table Data Structures

2.

If we have a cache memory of size 128KB, where each cache line is 64 bytes, we will have a total of 128k/64 = 2048 cache lines

To index 2048 cache lines we need 11 bits

11 bits used for index (identifies the cache line within the cache)

The upper 15 bits used for tag (matches the decoded address in RAM if data is in cache).

The lower 6 bits considered the offset into the cache line.

Question 1

In the cache example above, how many bits of the address line is required to map the data in cache line to the memory blocks in the RAM?

Question 2

How many 32 bit registers you would need in the cache controller to manage this 128KB cache. i.e:

Determine if it is a cache hit or miss, valid or invalid, dirty or clean

Every cache block has associated with a tag address