TASK $1$: Digital Electronics

Using the Logic Analyzer A logic analyzer is the digital equivalent of the oscilloscope used in the analog world. It is used to observe the value of the digital signals on wires over time. The logic analyzer is essential for debugging any digital circuit.

For a primary use of the logic analyzer, you can try a primary digital circuit as follows:

Design, enter, and simulate a circuit, using both schematic entry and Verilog as the design entry method $($i$.$e$.$ do it twice, with the two forms$),$ that implements the two logic functions, f$1,$ and f$2,$ with four inputs named a$,$ b$,$ c and d$.$

i$.$ The function f$1$ should be $1$ when either a $=$ c or b $=$ d$,$ but not when both a $=$ c and b $=$ d$.$

ii$.$ The function f$2$ should be $1$ when the number of $1$s in a$,$ b$,$ c and d is even. $($That is$,$ count the number of $1$s in the four variables; if the count is even, then f$2$ is $1,$ otherwise, it is $0.)$

Give the truth tables for functions f$1$ and f$2.$ Then derive a Boolean expression in canonical sum$-$of products $($canonical sum$-$of$-$products means the sum of min$-$terms only$)$ form for each function. Use algebraic manipulation to simplify the expressions.

Enter the simplified Boolean expressions into Quartus II in two different ways:

i$.$ Draw a schematic that includes the logic gates for both f$1$ and f$2.$

ii$.$ Write Verilog code representing f$1$ and f$2$ with Boolean equations.

Use the logic analyzer to observe time$-$varying digital signals of the circuit, do the following:

$1.$ Output the $50$MHz clock $($CLOCK$\_50)$ on the DE$2$ board to a GPIO pin $($i$.$e$.$ GPIO$\_0[0])$ on JP$1.$ The location of JP$1$ is shown in Figure $1.$ The pin assignments for the GPIO pins can be found in the repository for pin assignment files.

$2.$ Connect the $50$MHz clock to the input from one of the inputs from part $2$ of the preparation. Use the logic analyzer to observe both outputs $($f$1$ and f$2)$ of that circuit