Task

$2$

The ALU design will be simplified for this assignment. The block diagram of the ALU that you are required to design is given in Figure $2.$

In this group project, you will design the arithmetic logic unit $($ALU$)$ part of the Reduced Instruction Set Architecture $($RISC$-$V$)$ CPU. The CPU is currently one of the most widely used processors in low power embedded systems. The top$-$level block diagram of the RISC$-$V CPU is given in Figure $1.$

Figure I: KISC$-$V CPU architecture. The ALU component is highlighted in the dashed $($green$)$ bounding box.

$3.$

Design steps

Start with the design of the full adder gate$-$level schematic. Verify the correct functionality of the design by using the software simulation.

Instantiate the full adder in step $1$ to obtain a $4-$bit full adder and a $4-$bit subtractor. Ignore the final bit carry out from the adder and subtractor. Verify the correct functionality of the design by using the software simulation.

Design and verify a $1-$bit $41$ multiplexer.

Instantiate the mux in step $3$ to obtain a $4-$bit $41$ multiplexer.

Integrate the multiplexers, adder, subtractor, as well as the register to obtain the ALU design in Figure $2.$ For the register, use the component as shown in Figure $3.$ Note that you will need to instantiate $41-$bit DFF to obtain a $4-$bit DFF$.$ All other components $($mux$,$ adder, subtractor$)$ should be designed using basic gates.

Verify the correct functionality of your ALU design by using several possible input values.

The ALU specifications are:

The inputs are $A0,A1,A2,A3,B0,B1,B2,$ and $B3$ which are $4-$bits each; $B_{?}$Sel and $A_{S}el$ which are $2-$bits each; Alu$\_$op$,$ clock and reset which are $1-$bit each.

The output is Alu$\_$out which is $4-$bits. Ignore the final bit carry out signal in the adder.

The ALU operation is according to Table I:

Table $1$: ALU operation selector based on Alu$\_$op$.$

$\backslash$table$[[$Alu$\_$op$,$Operation$],[0,4-$bit adder, A $+$ B$],[1,4-$bit subtractor, A $-$ B$]]$

You are required to perform a modular design of the ALU given in Figure $2$ with the given specifications above. The design should use schematic based entry using logic gates for all components, except the register. The goal is to obtain a design that uses the least number of logic gates.

please use pen and paper to solve it use deeds