Task Breakdown

$1-$ D Flip$-$Flop

You will create a simplified version of logic.ly$\text{'}$s built$-$in D Flip$-$Flop, as seen in Figure $2.$ You should use the logic that is used in Figure $2($a$),$ except you should:

$1.$ remove the $\backslash (\backslash$mathrm$\{$Q$\}^\{\backslash$prime$\}\backslash )$ output

$2.$ remove the CLR$\text{'}$ inputs

$3.$ convert the PRE' input to PRE$\_$IN and add a PRE$\_$OUT output so that you can pass this signal to other flip$-$flops such that a single switch can reset multiple flip$-$flops, when needed

$4.$ downgrade $3-$input gates to $2-$input gates, where necessary $($due to the removal of CLR$\text{'})$

$5.$ add a CLK$\_$OUT signal $($which will make your wiring cleaner for the next stages$)$

$6.($recommended$)$ arrange the I$/$O$\text{'}$s as seen in Figure $2($c$)($Top: D$,$ Bottom: Q$,$ Left: $>,$ PRE$\_$IN$,$ Right: CLK$\_$OUT, PRE$\_$OUT$)$ for easiest tiling $($you can change the I$/$O sides if it suits your design$)$

NOTE: The D Flip$-$Flop implementation in the slides does not seem to work reliably in logic.ly$.$

Your custom component should have the following I$/$Os:

$-$ Inputs:

$-$ D $>($CLK$\_$IN$)*$PRE$\_$IN

$-$ Outputs:

$-$ Q CLK$\_$OUT $*$PRE$\_$OUT

NOTE: YOu will NOT be able to generate a truth table for this circuit since there are circular references.

$*$ Note that PRE$\_$IN and PRE$\_$OUT are added as I$/$Os throughout this project. The intention is that you can have one toggle switch at the outer most level that can keep getting passed through subcomponents that have flip$-$flops so you only need to toggle one switch to reset ALL the flip flops.

$($a$)$

$($b$)$

$($c$)$

Figure $2$: Logic.ly$\text{'}$s built$-$in D Flip$-$Flop $($a$)$ Boolean design and $($b$)$ standard cell. Your new standard cell $($c$),$ where CLR$\text{'}/$PRE$\text{'}/$Q$\text{'}$ have been removed and PRE$\_$IN $($formerly called PRE'$)$ and PRE$\_$OUT have been added, for simplicity.