TASKI $(20$ pts$\mathrm{.}1$: Design a Verilog model to implement the behavior described by the $4-$input minterm list below. Use procedural assignment and an if$-$else statement. Declare the module to match the block diagram provided. Use the type wire for the inputs and type reg for the output. Have your test bench change the input pattern every $40$ n using delay within the procedural block and simulate your design to verify the functionality using Modelsim$$M