Question: TASK 1 [ 2 0 pts . ] : Design a Verilog model to implement the behavior described by the 4 - input minterm list

TASK

1 [20

pts

.]

: Design a Verilog model to implement the behavior described by the

4 -

input minterm list below. Use procedural assignment and an if

-

else statement. Declare the module to match the block diagram provided. Use the type wire for the inputs and type reg for the output. Write a testbench and simulate your design to verify the functionality using Modelsim

.

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