tDocument ElementsTables Charts SmartArt Review Styles Insert 16 Styles Text Box 21 Draw a state diagram for an FSM that has an input A and an output Z. Whenever A changes from 0 to 1, 2 should become 1 for one clock cycle and then a zero for the next clock cycle independent of the value of input A. Only when input A does returns to "o", should Z return to the initial reset state. (20pts) 2. Print Layout vio Sec 1Pages, 30t 6 words 2 24 or 691