Question: TEST The verilog Code using a Testbench. I've copied my codes please follow the same stile and modify it so it works. You will need
TEST The verilog Code using a Testbench. I've copied my codes please follow the same stile and modify it so it works. You will need to the perform the operations in the table shown below in your test bench ALUtb and paste the waveforms showing successful operations.
Code:
ALU
module ALU input : aluina aluinb OPCODE, input Cin, output reg : Sum, output reg Cout, output OF;
reg : Bin;
wire : Bn S;
wire Co;
coms Caluinb Bn;
rippleadderbit FAaluina Bin, Cin, S Co OF;
always @ begin
Bin b; Sum b; Cout b;
case OPCODE
ALU operations
ABCin : add with Cin
b : begin
Bin aluinb; Sum S; Cout Co;
end
AB : add
b : begin
Bin aluinb; Sum S; Cout Co;
end
AB : sub a from b
b : begin
Bin Bn; Sum S; Cout Co;
end
aluina&aluinb : bitwise NAND
b : begin
Sum ~aluina & aluinb;
end
~aluinaaluinb : bitwise OR
b : begin
Sum aluina aluinb;
end
aluinaaluinb : bitwise XOR
b : begin
Sum aluinaaluinb;
end
Bitwise NOT a
b : begin
Sum ~aluina;
end
Bitwise NOT a
b : begin
Sum ~aluina;
end
Logical Shift a right Bit
b : begin
Sum aluina ;
end
default : begin
Sum ; Cout ;
end
endcase
end
endmodule
Bit Ripple Carry Adder
module rippleadderbitinput : A B input Cin,output : Sum, output Cout, OF;
fulladder FASum Cout A B Cin;
fulladder FASum Cout A B Cout;
fulladder FASum Cout A B Cout;
fulladder FASum Cout, A B Cout;
xor XOF Cout Cout;
endmodule
Twos Compliment
module coms input : B output : Bn;
wire : Bn;
wire OF;
assign Bn ~B;
rippleadderbit FABnbb Bn Cout, OF;
endmodule
Full Adder
module fulladderoutput S Cout, input A B Cin;
wire Sum Cout Cout;
halfadder HASum Cout A B;
halfadder HAS Cout Sum Cout;
or OCout Cout Cout;
endmodule
Half Adder
module halfadderoutput Sum, Cout, input AB;
assign Sum AB;
assign Cout A&B;
endmodule
Te Test Bench Lab
module tbalu;
Inputs
reg : aluina;
reg : aluinb;
reg : OPCODE;
reg Cin;
Outputs
wire : Sum;
wire Cout;
wire OF;
ALU module
ALU uut aluinaaluinaaluinbaluinbOPCODEOPCODECinCinSumSum
CoutCoutOFOF;
Addition
initial begin
aluina b;
aluinb b;
OPCODE b;
Cin b;
#;
$displaySum b Sum; Output: #
Addition With Cin
aluina b;
aluinb b;
OPCODE b;
Cin b;
#;
$displaySum b Sum; Output: #
Subtraction
aluina b;
aluinb b;
OPCODE b;
Cin b;
#;
$displaySum b Sum; Output:
Bitwise NAND
aluina b;
aluinb b;
OPCODE b;
Cin b;
#;
$displaySum b Sum;
Bitwise OR
aluina b;
aluinb b;
OPCODE b;
Cin b;
#;
$displaySum b Sum;
Bitwise XOR
aluina b;
aluinb b;
OPCODE b;
Cin b;
#;
$displaySum b Sum;
Bitwise NOT
aluina b;
aluinb b;
OPCODE b;
Cin b;
#;
$displaySum b Sum;
Logical Right shift
aluina b;
aluinb b;
OPCODE b;
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