Question: / / testbench.sv module fsm _ tb; reg clk; reg rst; reg A; reg [ 1 : 0 ] PS _ LOAD; wire z; wire

// testbench.sv
module fsm_tb;
reg clk;
reg rst;
reg A;
reg[1:0] PS_LOAD;
wire z;
wire[1:0] NS;
fsm uut (
.clk(clk),
.rst(rst),
.A(A),
.PS_LOAD(PS_LOAD),
.Z(Z),
.NS(NS)
);
initial begin
clk =0;
forever #5 clk = ~clk;
end
initial begin
rst =1;
#10
rst =0;
// Test loading different present states and read next states
PS_LOAD = s0;
#10;
$display ("Present state: %b, Next state: %b", PS_LOAD, NS);
PS_LOAD = s1;
#10;
$display ("Present state: %b, Next state: %b", PS_LOAD, NS);
PS_LOAD = s2;
#10;
$display ("Present state: %b, Next state: %b", PS_LOAD, NS);
PS_LOAD = s3;
#10;
$display ("Present state: %b, Next state: %b", PS_LOAD, NS);
end
endmodule Parsing design file '
design.sv'
Error-[IND] Identifier not declared
design.sv,31
Identifier 's4' has not been declared yet. If this error is not expected,
please check if you have set 'default_nettype to none.
Parsing design file '
testbench.sv'
Error-[IND] Identifier not declared
testbench.sv,31
Identifier 's0' has not been declared yet. If this error is not expected,
please check if you have set 'default_nettype to none.
Error-[IND] Identifier not declared
testbench. 5v,35
Identifier 's1' has not been declared yet. If this error is not expected,
please check if you have set 'default_nettype to none.
Error-[IND] Identifier not declared
testbench.sv,39
Identifier 's2' has not been declared yet. If this error is not expected,
please check if you have set 'default_nettype to none.
Error-[IND] Identifier not declared
testbench.sv,43
Identifier '53' has not been declared yet. If this error is not expected,
please check if you have set 'default_nettype to none.
5 errors
CPU time: .146 seconds to compile
Exit code expected: 0, received: 255// design.sv
module fsm (
input clk,
input rst,
input A,
input[1:0] PS_LOAD, // input to load present state
output reg Z,
output reg[1:0] NS // output to read next state
);
parameter[1:0] s0=2'b00;
parameter[1:0] s1=2'b01;
parameter[1:0] s2=2'b10;
parameter[1:0] s3=2'b11;
reg[1:0] PS;
always@ (posedge clk) begin
if (rst) begin
PS = s0;
end else begin
PS = PS_LOAD; // load desired present state
end
end
always@ (PS, A) begin
case ({PS,A})
{s0,0} :begin NS = s3; Z =0; end
{s0,1} :begin NS = s2; Z =1; end
{s1,0} :begin NS = s3; Z =1; end
{s1,1} :begin NS = s4; Z =0; end
{s2,0} :begin NS = s3; Z =1; end
{s2,1} :begin NS = s4; Z =0; end
{s3,0} :begin NS = s4; Z =0; end
{s3,1} :begin NS = s1; Z =1; end
{s4,0} :begin NS = s4; Z =1; end
{s4,1} :begin NS = s1; Z =1; end
endcase
end
endmodule Image shows error messages. Respond asap.
// testbench.sv module fsm_tb; reg clk; reg rst; reg A; reg[1:0]

Step by Step Solution

There are 3 Steps involved in it

1 Expert Approved Answer
Step: 1 Unlock blur-text-image
Question Has Been Solved by an Expert!

Get step-by-step solutions from verified subject matter experts

Step: 2 Unlock
Step: 3 Unlock

Students Have Also Explored These Related Databases Questions!

Q:

` ttimescale 1 ns / 1 ps module tb ( ) ; reg clk = 0 ; wire [ 2 : 0 ] floor; reg rst = 0 ; reg [ 2 : 0 ] button _ value = 0 ; reg button _ pressed = 0 ; reg error = 0 ; initial begin rst = 1 ; @ (...

Q:

I have posted the code and test bench for the following: please help me get it waveform on vivado. i am getting some errors. main code: 16 bit risc mips -------------------------------------------...

Q:

I have posted the code and test bench for the following: please help me get it waveform on vivado. i am getting some errors. ------------------------ // main code: 16 bit risc mips processor...

Q:

` timescale 1 ns / 1 ps module TestBenchForCache; / / Inputs reg clk; reg reset; reg [ 3 1 : 0 ] read _ data; / / Outputs wire [ 3 1 : 0 ] pc; wire [ 3 1 : 0 ] alu _ result; wire [ 3 1 : 0 ] write _...

Q:

` timescale 1 ns / 1 ps module TestBenchForCache; / / Inputs reg clk; reg reset; reg [ 3 1 : 0 ] read _ data; / / Outputs wire [ 3 1 : 0 ] pc; wire [ 3 1 : 0 ] alu _ result; wire [ 3 1 : 0 ] write _...

Q:

is it easier if it start arithmode then press the button to switch the mode to bitwise? module calculator _ fsm ( input clk , input btn _ mode, / / Button for toggling modes input [ 1 : 0 ] btn _...

Q:

Why doesn't my code load anything onto the registers. module Control _ Circuit ( input clk , input rst , input [ 1 5 : 0 ] instruction, output [ 7 : 0 ] Rin, output [ 7 : 0 ] Rout, output [ 1 : 0 ]...

Q:

please provide a code solutiontionwhy does my simulation have errors module outputter ( input [ 3 : 0 ] state, input [ 1 5 : 0 ] instruction, output reg [ 1 0 : 0 ] Rin, output reg [ 1 0 : 0 ] Rout,...

Q:

Taylor series is one of well-known methods to compute mathematical functions such as 1/x, log(x), exp and etc. In this homework, you are provided with the Verilog code of a sequential circuit that...

Q:

Below is the BASE implementation of the MIPSzy's processor design in Verilog code. Extend the base implementation to support MIPS instructions including sub, j, slt, beq, jal, jr. I started the CTRL,...

Q:

Fresh numbers from the U.S. Department of Transportation suggest that fewer lights in the U.S. arrive on time than before. The explanations offered for the lackluster performance are understaffed...

Q:

What is WTO? What led to its organization? Describe briefly its salient features.

Q:

[ In one paragraph, describe the Johnson & Johnson likely future financial performance based on its latest financial well - being and risk level. Use financial information to support your claims. ]

Q:

i need correct answrrs 3 6 2 .

Q:

Imagine that the U.S. Congress, recognizing the importance of being well dressed, started giving preferential tax treatment to clothing insurance. Under this new type of insurance, you would pay the...

Q:

Find some information on an index fund (such as the Vanguard Total Stock Market Index, ticker symbol VTSMX). How has this fund performed compared with other stock mutual funds over the past 5 or 10...

Q:

According to an old myth, Native Americans sold the island of Manhattan about 400 years ago for $24. If they had invested this amount at an interest rate of 7 percent per year, how much would they...