Question: please provide a code solutiontionwhy does my simulation have errors module outputter ( input [ 3 : 0 ] state, input [ 1 5 :

please provide a code solutiontionwhy does my simulation have errors module outputter(
input [3:0] state,
input [15:0] instruction,
output reg [10:0] Rin,
output reg [10:0] Rout,
output reg [1:0] addSub
);
reg [3:0] triReg, RegEnable;
// Internal wires for one-hot encoding
wire [10:0] triStateWires, enableWires;
// Instantiate oneHot modules
oneHot writeDemux(.select(RegEnable),.out(triStateWires));
oneHot readDemux(.select(triReg),.out(enableWires));
// State machine to control Rin, Rout, and addSub
always @(state or instruction) begin
triReg =4'b0000; // Default no output enable
RegEnable =4'b0000; // Default no register enable
addSub =2'b00; // Default add operation
case(state)
4'b0001: begin // Load
triReg =4'b1010; // Data triReg enable
RegEnable = instruction[11:8]; // Rxin enable
end
4'b0010: begin // Move
triReg = instruction[7:4]; // Rxout
RegEnable = instruction[11:8]; // Ryin
end
4'b0011: begin // Add/Sub/Xor first state
triReg = instruction[11:8]; // Rxout
RegEnable =4'b1000; // Ain
end
4'b0100: begin // Add middle state
triReg = instruction[7:4]; // Ryout
RegEnable =4'b1001; // Gin
addSub =2'b00; // add
end
4'b0110: begin // Sub middle state
triReg = instruction[7:4]; // Ryout
RegEnable =4'b1001; // Gin
addSub =2'b01; // sub
end
4'b0111: begin // Xor middle state
triReg = instruction[7:4]; // Ryout
RegEnable =4'b1001; // Gin
addSub =2'b10; // xor
end
4'b0101: begin // Add/Sub/Xor last state
triReg =4'b1001; // Gout
RegEnable = instruction[11:8]; // Ryin
end
default: begin
triReg =4'b0000;
RegEnable =4'b0000;
addSub =2'b00;
end
endcase
end
// Assign outputs from the oneHot module results
always @(*) begin
Rin = triStateWires;
Rout = enableWires;
end
endmodule
module Control_Circuit (
input clk,
input rst,
input [15:0] instruction,
output [10:0] Rin,
output [10:0] Rout,
output [1:0] addSub
);
wire [3:0] current_state;
wire [3:0] next_state;
reg [3:0] state_reg;
// Instantiate Next_State FSM
Next_State fsm (
.instruction(instruction),
.current_state(current_state),
.next_state(next_state)
);
outputter asd (
.state(current_state),
.instruction(instruction),
.Rin(Rin),
.Rout(Rout),
.addSub(addSub)
);
// Register to hold the current state
always @(posedge clk or posedge rst) begin
if (rst)
state_reg <=4'b0000; // Initial state
else
state_reg <= next_state;
end
assign current_state = state_reg;
endmodule
module tristatebuffer (
input [15:0] a,
output reg [15:0] b,
input enable
);
always @(*)
begin
if (enable)
b = a;
else
b =16'bZ; // tri-state
end
endmodule
module oneHot(select, out);
input [3:0] select;
output reg [10:0] out;
always @(select) begin
out =11'b00000000000; // Default value to avoid latches
case (select)
4'b0000 : out =11'b00000000001;
4'b0001 : out =11'b00000000010;
4'b0010 : out =11'b00000000100;
4'b0011 : out =11'b00000001000;
4'b0100 : out =11'b00000010000;
4'b0101 : out =11'b00000100000;
4'b0110 : out =11'b00001000000;
4'b0111 : out =11'b00010000000;
4'b1000 : out =11'b00100000000;
4'b1001 : out =11'b01000000000;
4'b1010 : out =11'b10000000000;
endcase
end
endmodule
module Next_State (
input [15:0] instruction,
input [3:0] current_state,
output reg [3:0] next_state
);
always @(*) begin
case (current_state)
4'b0000: begin
case (instruction[15:12])
4'b0000: next_state =4'b0001; // Load
4'b0001: next_state =4'b0010; // Move
4'b0010: next_state =4'b0011; // Add/Sub/Xor - first state
4'b0011: next_state =4'b0011; // Add/Sub/Xor - first state
4'b0100: next_state =4'b0011; // Add/Sub/Xor - first state
default: next_state =4'b0000; // Default state
endcase
end
4'b0001: next_state =4'b0000; // Return to initial after Load
4'b0010: n
\table[[8.,Msgs,,,,,,,],[/tb_processor/ck,1'h1,,\sqrt,L,,,,],[/tb_processor/rst,1'h0,,,,,,,],[+/tb_processor/instr...,16h4340,\sqrt1010\sqrt1

Step by Step Solution

There are 3 Steps involved in it

1 Expert Approved Answer
Step: 1 Unlock blur-text-image
Question Has Been Solved by an Expert!

Get step-by-step solutions from verified subject matter experts

Step: 2 Unlock
Step: 3 Unlock

Students Have Also Explored These Related Databases Questions!

Q:

Implement the following circuit using the modules that you have implemented in PART 1 . For FFs , you should use one single synchronous reset. You have 5 input ports, i . e . X , Y , Z , S 0 , S 1...

Q:

The following algorithm is used to find the integer square root for an input integer number x [ Ex 1 : if n { 4 , 5 , 6 , 7 , 8 } , then the result integer square ? Y = 2 ] [ Ex 2 : if n { 9 , 1 0 ,...

Q:

THE REQUIREMENTS DOCUMENTS ARE AS FOLLOWS: PLEASE PROVIDE OP CODE TABLE & MACHINE CYCLE DIAGRAM IN EXCEL OR PDF Either Word, Visio, PDF, or any acceptable format that clearly shows a block diagram of...

Q:

testbench.sv module testCPU; reg clk , reset; wire [ 7 : 0 ] DMem; int errors = 0 ; reg [ 7 : 0 ] DMem _ expected [ 4 : 0 ] ; integer i , j; top _ CPU CPU 0 ( . D _ rd _ data ( DMem ) , . clk ( clk )...

Q:

Here is the code template we were provided to finish the code on. (Only need to write code where it says "Replace this comment" which means only 4 blocks of small code need to be written. Everything...

Q:

Here is the Code Template we were provided to use. (Only got to put code where it says "Replace this comment block". Everything else is given pretty much) `timescale 1ns / 1ps...

Q:

//Tester module sends a periodic clock signal to the flip-flop module tester(q,qn,clk,d, A , B, ALUctl); input q,qn; output clk,d; //A, B, ALUctl; output [3:0] A, B, ALUctl; reg clk,d, A, B, ALUctl;...

Q:

//Tester module sends a periodic clock signal to the flip-flop module tester(q,qn,clk,d, A , B, ALUctl); input q,qn; output clk,d; //A, B, ALUctl; output [3:0] A, B, ALUctl; reg clk,d, A, B, ALUctl;...

Q:

The new line character is utilized solely as the last person in each message. On association with the server, a client can possibly (I) question the situation with a client by sending the client's...

Q:

Our first analysis will be to satisfy Mrs. Adebambo's view of revenue by productline - so we have to produce a pie chart with the Cumulation of revenue by productline from Salesview Secondly we are...

Q:

Does the executive summary describe the key elements needed in a business plan? Is the proposed offer well written, why or why not? What are the important marketing issues and competitive advantages?...

Q:

A symptom validity test (SVT) is sometimes used to confirm diagnosis of psychiatric disorders. The paper Developing a Symptom Validity Test for Posttraumatic Stress Disorder: Application of the...

Q:

Which of the following statements is true in the context of diversification? As long as the return on different investments is not perfectly positively correlated, financial intermediaries can...

Q:

If capacity is excessive, a company may have to _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . Group of answer choices decide how to use a partially empty facility outsource use group technology raise...

Q:

clarify and articulate your research methodology;

Q:

focus your project by developing a research aim and research objectives or questions;

Q:

consider how to build on prior learning.