test_bench.v.

//----------------------------------------------------------------------------- // Title : MIPS Pipelined Processor // Project : ECE 313 - Computer Organization //----------------------------------------------------------------------------- // File : mips_single.v // Author : John Nestor // Organization : Lafayette College // // Created : October 2002 // Last modified : 7 January 2005 //----------------------------------------------------------------------------- // Description : // Pipelined implementation of the MIPS processor subset described in // Section 6.3 of "Computer Organization and Design, 3rd ed." // by David Patterson & John Hennessey, Morgan Kaufmann, 2004 (COD3e). // // It implements the equivalent of Figure 6.27 on page 404 of COD3e // //-----------------------------------------------------------------------------

module test_bench (); reg clk, reset; wire halt; parameter FILE = "test1.dat"; mips_pipeline dut(clk, reset, halt);

// initialize test initial begin reset

// generate clock to sequence tests always begin if ( halt == 1'b1 ) begin $stop; end clk

endmodule

Part A: Warming Up! To warm up, just run simulation with the code we provide, and answer the following two questions. 1. (test1.dat) How many clock cycles does it take to execute the binary? de HALT instruction) 2. at) Find and explain all hazards that would occur if there were no NOPs. module test bench 0: reg ck, reset: Darameter FLE 'test 1.dBI NOTE mips pipeline dut(clk, reset, halt): initialize test initial You can change test instruction set by changing FILE parameter in begin reset 1: 23: reset test bench.v". generate clock to secuence tests always begin b1) if halt begin $stop. end Part A: Warming Up! To warm up, just run simulation with the code we provide, and answer the following two questions. 1. (test1.dat) How many clock cycles does it take to execute the binary? de HALT instruction) 2. at) Find and explain all hazards that would occur if there were no NOPs. module test bench 0: reg ck, reset: Darameter FLE 'test 1.dBI NOTE mips pipeline dut(clk, reset, halt): initialize test initial You can change test instruction set by changing FILE parameter in begin reset 1: 23: reset test bench.v". generate clock to secuence tests always begin b1) if halt begin $stop. end