Question: The basic D Flip - Flop has a D ( data ) input, a clock input, and a Q output. Optionally
The basic D FlipFlop has a data input, a clock input, and a output. Optionally it may also include a PR Preset and a CLR Clear control input. Since the input does not have an effect on the value of output until a clock signal rising or falling edge is received, the input is considered synchronous. The optional signals PR and CLR are asynchronous because they can affect the output regardless of the clock signal. In digital logic and computing, a Counter is a device which stores and sometimes displays the number of times a particular event or process has occurred, often in relationship to a clock. The most common type is a sequential digital logic circuit with an input line called the clock and multiple output lines. The values on the output lines represent a number in the binary or BCD number system. Each pulse applied to the clock input increments or decrements the number in the counter. Counters are a very widely used component in digital circuits and are also incorporated as parts of larger integrated circuits. Description: For this lab, design, synthesize, and functionally verify a sequential logic circuit Synchronous Counter that displays the even values of a bit binary input. Use DFlip Flop dff Use a bit counter to generate the binary values. The count sequence should start with and end with skipping every odd value. It will also restart with binary after is reached Decimal: The Binary values shall be displayed using the LEDs LEDR LEDR A bit LPMCounter module from the IP Catalog must be used to control the clock input to the counter. The counter circuit must also have an active LOW asynchronous clear input switch SW to reset the counter to Make sure to compare the simulation results, the Boolean expressions, and the truth tables with the development board functionality. Use the Waveform Viewer for functional verification and physically test using the DELite development board.
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