Question: The basic pipeline for DLX has five stages IF, ID, MEM, and WB. Assuming all memory access takes 1 clock cycle What is the control

The basic pipeline for DLX has five stages IF, ID, MEM, and WB. Assuming all memory access takes 1 clock cycle

What is the control hazard of an instruction pipeline? Provide three branches of prediction alternatives to reduce branch hazard

What is the data forwarding scheme used to reduce the data hazard?

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