The basic pipelined MIPS is illustrated in Figure 3. Go over it rigorously and then type/write the input vectors of the four pipeline registers in the space provided below. To create the vectors, use ' & ', the concatenation operator. Note that the MSb of each pipeline register is located on the top, as shown in Figure 3. In your VHDL model, the input signals of each pipeline register should have the same order that you see in this figure: Ifsedpein