Question: The circuit for this VHDL code entity latch is port (q, qb : buffer BIT ; r,s : in BIT); end entity latch; architecture gate

The circuit for this VHDL code

entity latch is port (q, qb : buffer BIT ; r,s : in BIT); end entity latch; architecture gate of latch is begin gO: entity WORK. nand2 port map (q,qb,r); g1: entity WORK . nand2 port map (qb, q,s ) ; end architecture gate

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