Question: The code bellow is a modified version of the TI sample code for a multi channel ADC Converter and UART communication I am having trouble
The code bellow is a modified version of the TI sample code for a multi channel ADC Converter and UART communication I am having trouble getting this code to work and im not sure what I am doing wrong advice and critique is much appreciated. I believe it has to do with trying to merge the UART ISR and the ADC ISR as well as my output Variables...
#include #define Num_of_Results 8 unsigned int ADC_data0 = 0; unsigned char LSB_data0 = 0; unsigned char MSB_data0 = 0; unsigned int ADC_data1 = 0; unsigned char LSB_data1 = 0; unsigned char MSB_data1 = 0; unsigned int ADC_data2 = 0; unsigned char LSB_data2 = 0; unsigned char MSB_data2 = 0; volatile unsigned int A0results[Num_of_Results]; volatile unsigned int A1results[Num_of_Results]; volatile unsigned int A2results[Num_of_Results]; //volatile unsigned int A3results[Num_of_Results]; int main(void) { WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer P6SEL = 0x0F; // Enable A/D channel inputs ADC12CTL0 = ADC12ON+ADC12MSC+ADC12SHT0_8; // Turn on ADC12, extend sampling time // to avoid overflow of results ADC12CTL1 = ADC12SHP+ADC12CONSEQ_3; // Use sampling timer, repeated sequence ADC12MCTL0 = ADC12INCH_0; // ref+=AVcc, channel = A0 ADC12MCTL1 = ADC12INCH_1; // ref+=AVcc, channel = A1 ADC12MCTL2 = ADC12INCH_2+ADC12EOS; // ref+=AVcc, channel = A2 // ADC12MCTL3 = ADC12INCH_3+ADC12EOS; // ref+=AVcc, channel = A3, end seq. ADC12IE = 0x04; // Enable ADC12IFG.3 ADC12CTL0 |= ADC12ENC; // Enable conversions ADC12CTL0 |= ADC12SC; // Start convn - software trigger //UART setup P3SEL |= BIT3+BIT4; // P3.3,4 = USCI_A0 TXD/RXD UCA0CTL1 |= UCSWRST; // **Put state machine in reset** UCA0CTL1 |= UCSSEL_2; // SMCLK UCA0BR0 = 9; // 1MHz 115200 (see User's Guide) UCA0BR1 = 0; // 1MHz 115200 UCA0MCTL |= UCBRS_1 + UCBRF_0; // Modulation UCBRSx=1, UCBRFx=0 UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine** UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt while (1) //tell adc to take a reading { ADC12CTL0 |= ADC12SC; // Start sampling/conversion __bis_SR_register(LPM0_bits + GIE); // LPM0, ADC12_ISR will force exit MSB_data0 = (unsigned char)(ADC_data0>>8); LSB_data0 = (unsigned char)ADC_data0; MSB_data1 = (unsigned char)(ADC_data1>>8); LSB_data1 = (unsigned char)ADC_data1; MSB_data2 = (unsigned char)(ADC_data2>>8); LSB_data2 = (unsigned char)ADC_data2; // if (ADC_data >= 0x7ff) // ADC12MEM = A0 > 0.5AVcc? (greater than 50% of scale, if it is led on, else led off) // P1OUT |= BIT0; // P1.0 = 1 // else // P1OUT &= ~BIT0; // P1.0 = 0 __no_operation(); // For debugger } // For debugger } #if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) #pragma vector=ADC12_VECTOR __interrupt void ADC12ISR (void) #elif defined(__GNUC__) void __attribute__ ((interrupt(ADC12_VECTOR))) ADC12ISR (void) #else #error Compiler not supported! #endif { static unsigned int index = 0; switch(__even_in_range(ADC12IV,34)) { case 0: break; // Vector 0: No interrupt case 2: if (UCA0RXBUF ==82){ //82 decimal is R in ASCII while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready? UCA0TXBUF = LSB_data0; //UCA0TXBUF = UCA0RXBUF; // TX -> RXed character while (!(UCA0IFG&UCTXIFG)); UCA0TXBUF = MSB_data0; } __no_operation(); break; // Vector 2: ADC overflow case 4: break; // Vector 4: ADC timing overflow case 6: break; // Vector 6: ADC12IFG0 case 8: break; // Vector 8: ADC12IFG1 case 10: // Vector 10: ADC12IFG2 A0results[index] = ADC12MEM0; // Move A0 results, IFG is cleared A1results[index] = ADC12MEM1; // Move A1 results, IFG is cleared A2results[index] = ADC12MEM2; // Move A2 results, IFG is cleared //A3results[index] = ADC12MEM3; // Move A3 results, IFG is cleared A0results[index] = ADC_data0; A1results[index] = ADC_data1; A2results[index] = ADC_data2; index++; // Increment results index, modulo; Set Breakpoint1 here if (index == 4) { (index = 0); } case 12: // Vector 12: ADC12IFG3 // A0results[index] = ADC12MEM0; // Move A0 results, IFG is cleared // A1results[index] = ADC12MEM1; // Move A1 results, IFG is cleared // A2results[index] = ADC12MEM2; // Move A2 results, IFG is cleared //A3results[index] = ADC12MEM3; // Move A3 results, IFG is cleared // index++; // Increment results index, modulo; Set Breakpoint1 here // if (index == 4) // { // (index = 0); // } break; case 14: break; // Vector 14: ADC12IFG4 case 16: break; // Vector 16: ADC12IFG5 case 18: break; // Vector 18: ADC12IFG6 case 20: break; // Vector 20: ADC12IFG7 case 22: break; // Vector 22: ADC12IFG8 case 24: break; // Vector 24: ADC12IFG9 case 26: break; // Vector 26: ADC12IFG10 case 28: break; // Vector 28: ADC12IFG11 case 30: break; // Vector 30: ADC12IFG12 case 32: break; // Vector 32: ADC12IFG13 case 34: break; // Vector 34: ADC12IFG14 default: break; } }
Study Help