The counting circuit should count the number of times each of the two signals produced by...

  

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The counting circuit should count the number of times each of the two signals produced by the detector circuit is asserted. It has two corresponding outputs: "UP" and "DOWN". If any of the input signals is detected 4 times the corresponding output should be set to 1 for whole clock cycle and the counting, for both signals, should reset. Both circuits above are controlled by a common clock. Implementation In order to realize the design specified above, you must completely specify the logical circuits that implement it. You are only allowed to use primitive gates (and, or, xor, ete) and Verilog. You need to do the following: 1. Determine the overall structure of the system and the needed functional units. 2. Inputs/outputs of each unit needed in the design 3. Block dingram showing the connetivity between the various units. 4. Complete design of each unit (this could be Verilog code or block diagrams). Up/Down Lever Down (send 1101) Up (send 1011) Detector Circuit d. Circuit DOWN i Counting Seriolus Other devices (door sensor, emergency brakes, etc) Figure 1: Block dingram of the lever controller circuit. The detector circuit This circuit has only one input wire, the serial bus s, and two outputs, the up signal u and the down signal d. The up signal, s, should only be 1 if the string 1011 is detected in the input, otherwise it will be 0. Similarly, d will only be 1 if the string 1101 is detected. The patters or strings will never overlap. For example, the input "0011011" contains the string 1101 but not 1011 because it overlaps with the previous string. In other words, you should reset the detection whenever a complete string is discovered. The counting circuit should count the number of times each of the two signals produced by the detector circuit is asserted. It has two corresponding outputs: "UP" and "DOWN". If any of the input signals is detected 4 times the corresponding output should be set to 1 for whole clock cycle and the counting, for both signals, should reset. Both circuits above are controlled by a common clock. Implementation In order to realize the design specified above, you must completely specify the logical circuits that implement it. You are only allowed to use primitive gates (and, or, xor, ete) and Verilog. You need to do the following: 1. Determine the overall structure of the system and the needed functional units. 2. Inputs/outputs of each unit needed in the design 3. Block dingram showing the connetivity between the various units. 4. Complete design of each unit (this could be Verilog code or block diagrams). Up/Down Lever Down (send 1101) Up (send 1011) Detector Circuit d. Circuit DOWN i Counting Seriolus Other devices (door sensor, emergency brakes, etc) Figure 1: Block dingram of the lever controller circuit. The detector circuit This circuit has only one input wire, the serial bus s, and two outputs, the up signal u and the down signal d. The up signal, s, should only be 1 if the string 1011 is detected in the input, otherwise it will be 0. Similarly, d will only be 1 if the string 1101 is detected. The patters or strings will never overlap. For example, the input "0011011" contains the string 1101 but not 1011 because it overlaps with the previous string. In other words, you should reset the detection whenever a complete string is discovered.

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