The critical path of a combinational circuit is shown below. Assume each gate is 1X and the
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The critical path of a combinational circuit is shown below. Assume each gate is 1X and the reference template is a 2/1 sized inverter. Let Cin = 5Cg, and CL = 100Cg. a
a) (10pts) Calculate the logical effort delay. b) (10pts) Now assume that each interconnect between two gates has a wire cap of Cg and repeat (a).
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