The CSA-based multiplier circuit (last version we saw in class) appears to be suboptimal. In particular, full adders in the first row have 0s as inputs whereas they could also have other inputs (e.g. a0 AND b2 and al AND b2 for the first two full adders, respectively). Doing more useful work earlier at no circuit cost should be an improvement. Try redrawing the circuit to maximize the number of full adders with three partial-product bit inputs (replacing a 0, a carry, or a sum from one or more of the full adder). Make sure it still works and that each FA has at most 3 inputs! Show your drawing. Does the timing change? The CSA-based multiplier circuit (last version we saw in class) appears to be suboptimal. In particular, full adders in the first row have 0s as inputs whereas they could also have other inputs (e.g. a0 AND b2 and al AND b2 for the first two full adders, respectively). Doing more useful work earlier at no circuit cost should be an improvement. Try redrawing the circuit to maximize the number of full adders with three partial-product bit inputs (replacing a 0, a carry, or a sum from one or more of the full adder). Make sure it still works and that each FA has at most 3 inputs! Show your drawing. Does the timing change