The diagram below shows the archite Multi-processor scheduling Tabeled Core N are processor cores and are caches. You can man about whether a cache belongs to a pr are two separate silicon dies which communicate through a bus called the the architecture of an AMD Threadripper 1950 processor. The boxes ocne belongs to a processor or is shared based on the way it is drawn. There afe caches. You can make some inferences es which communicate through a bus called the "infinity Fabric DIEO DIEN What type of multiprocessor scheduling algorithm would you run on a system using this processor? Please discuss: a) Number of queues b) Considerations of process placement on processors or migration, if applicable