the first problem focuses on collecting statistics for the average number of consumer instructions of each register, and then it proposes keeping most frequently accessed registers on a register cache at the decode stage so that we can improve processor performance. Remember that we assume each access takes 2 cycles on the register file and 1 cycle on the register cache. a. Propose two alternative designs, one for better power savings, in which the register cache and the register file are accessed sequentially, and one for better performance, in which the register cache and the register file are accessed in parallel. Show the details of your designs by drawing figures of the datapath structures, their interactions and their required connections. b. Using the Amdahl's Law, elaborate how much overall speedup we can gain when the frequency of use of the register cache is 100%,75%,50%,25% and 0%