The following algorithm is used to find the integer square root for an input integer number...

 

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The following algorithm is used to find the integer square root for an input integer number X [Ex1: if X = {4, 5, 6, 7, 8), then the result integer square root Y = 2 ] [Ex2: if XE {9, 10, 11, 12, 13, 14, 15), then the result integer square root Y = 3] Input: X (n-bit integer number) Output: Y = X Step1: Initialization A X (Input Data) Q=1 B = 3 step2: QQ + B step3: B= B + 2 repeat the last two steps (step 2 and step 3) until Q > A step4: Shift B one bit to the right (a logical shift) step5: Y = B-1 (The result) Complete the following Verilog code to provide a behavioral implementation for this algorithm. module SQRT_Calculator ( input CLK, input [9:0] X, output reg [4:0] Y Your design should include the following pins: 1. CLK: (negative edge trigger input clock) 2. X: The input number (10 bits) 3. Y: The result square root (5 bits) (Hint: define the variables A, B, and Q to be of size 11) The following algorithm is used to find the integer square root for an input integer number X [Ex1: if X = {4, 5, 6, 7, 8), then the result integer square root Y = 2 ] [Ex2: if XE {9, 10, 11, 12, 13, 14, 15), then the result integer square root Y = 3] Input: X (n-bit integer number) Output: Y = X Step1: Initialization A X (Input Data) Q=1 B = 3 step2: QQ + B step3: B= B + 2 repeat the last two steps (step 2 and step 3) until Q > A step4: Shift B one bit to the right (a logical shift) step5: Y = B-1 (The result) Complete the following Verilog code to provide a behavioral implementation for this algorithm. module SQRT_Calculator ( input CLK, input [9:0] X, output reg [4:0] Y Your design should include the following pins: 1. CLK: (negative edge trigger input clock) 2. X: The input number (10 bits) 3. Y: The result square root (5 bits) (Hint: define the variables A, B, and Q to be of size 11)

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Here is the Verilog code implementation for the given algorithm verilog module SQRTCalculator inp... View the full answer