The following assembly language program is being run on the $5$ stage AVR pipeline that we

studied in the lecture notes.

sub $r26,r2$

$1d5,Y$

$stx,r7$

add $r7,r5$

The program is run on four different AVR micro$-$architectures with the following capabilities:

Single cycle execution $($no pipeline capability$).$

Pipeline capability with stalling only.

Pipeline capability with forwarding only.

Pipeline capability with stalling used to enable forwarding.

a$)$ For each of the micro$-$architectures described above, draw a pipeline timeline diagram

for each of the assembly language instructions. If applicable, use arrows to indicate:

when forwarding occurs between stages on your pipeline diagrams. You do not have

to label your arrows.

b$)$ Determine the average latency $($in clock cycles$)$ and throughput $($in instructions$/$cycle$)$

for each of the micro$-$architectures described above. For a fair comparison, express

your answers in terms of clock cycles for the pipelined architectures. This means that

the single cycle architecture will require $5$ clock cycles to complete a full instruction.

Notes:

You can use this simpler format for your pipeline timeline diagrams:

Calculate throughput relative to the completion time of the first instruction. So$,$ for

your single cycle processor, your throughput calculation should be $\frac{3}{5+5+5}=0\mathrm{.}2$

instructions$/$cycle$.$