The following circuit is a $4-$input dynamic logic. $($a$)$ Identify the logic function for the output Z$.($b$)$ What input vector imposes the worst case charge sharing during the evaluation time? $($c$)$ Compute the final voltage at Z$,$ if the input vector is ABCDE$=11000$ during evaluation after charge sharing. Assume that Vtn $=0\mathrm{.}4$V$.($d$)$ Determine the width of the PMOS such that the maximum worst case precharge time delay $(0$ to $90\%)$ is limited to $250$ps$.($The worst case is when all the inputs are at VDD such that all the intermediate capacitors contribute to the delay$).$ Assume that VDD $=1\mathrm{.}2$ V$,$ K$$p $=50$ uA$/$V$2,$ and Vtp $=-0\mathrm{.}5$ V in the $100$nm technology node. For simplicity assume that the PMOS will stay in saturation during the transition.