The following circuit is a 4-bit parallel/serial load shift register with enable input. Shifting operation: s_1-0. Parallel load: s_1-1. Note that Q -03020100 D D3D2D,Do Write a structural VHDL code. You MUST create a file for: i) flip flop, ii) MUX 2-to-1, and i) top file (where you will interconnect the flip flops and MUXes). Provide a printout. 93 92 Q1 20 reset clk din D3 s_l D2 D1 DO clk resetn1 din 1011 1010 1100 0111 0101 2 0000 The following circuit is a 4-bit parallel/serial load shift register with enable input. Shifting operation: s_1-0. Parallel load: s_1-1. Note that Q -03020100 D D3D2D,Do Write a structural VHDL code. You MUST create a file for: i) flip flop, ii) MUX 2-to-1, and i) top file (where you will interconnect the flip flops and MUXes). Provide a printout. 93 92 Q1 20 reset clk din D3 s_l D2 D1 DO clk resetn1 din 1011 1010 1100 0111 0101 2 0000