The following code is to be run on the pipelined MIPS CPU which stalls on data hazards and does not

forward.

$1w$$$t1,0($$$a0)$

beq $t$1,$ $$0,$ targ$1$ #this branch is not taken

addi $$a0,$$$a0,4$

add $$t1,$$$t1,$$$t3$

$1w$$$t1,0($$$t1)$

add $$v0,$$$v0,$$$t1$

Show the pipeline timing on the diagrams for the following conditions. Use the two$-$

letter abbreviations for each stage: IF$,$ RF$,$ EX$,$ M$,$ WB

a$.$ Assume stalling for both control $($branch$)$ hazards and data hazards. For control

hazards, IF of the dependent $($later$)$ instruction aligns with WB of the earlier

instruction. For data hazards, RF of the dependent instruction must follow WB of

the earlier instruction.

Cycle

$0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,22,21,22$