The following code is to be run on the pipelined MIPS CPU which stalls on data hazards and does not forward 1. beg $t1, $0, targl #this branch is not taken addi a0, a0, 4 add $tl, Stl, St3 lw St1, 0 (St1) add SvO, $v0, $tl Show the pipeline timing on the diagrams for the following conditions. Use the two- letter abbreviations for each stage: IF, RF, EX, M, WB a. Assume stalling for both control (branch) hazards and data hazards. For control hazards, IF of the dependent (later) instruction aligns with WB of the earlier instruction. For data hazards, RF of the dependent instruction must follow WB of the earlier instruction Cycle 0 1 2 3 45 6 7 8 9 10 11 12 13 14 15 16 17 18 19 22 21 22 w $t1, 0(Sa0) beq St1, S0, targ1 addi $a0, $a0, 4 add $t1, $t1, $t3 w $t1, 0(St1) add Svo, $vO, t1 The following code is to be run on the pipelined MIPS CPU which stalls on data hazards and does not forward 1. beg $t1, $0, targl #this branch is not taken addi a0, a0, 4 add $tl, Stl, St3 lw St1, 0 (St1) add SvO, $v0, $tl Show the pipeline timing on the diagrams for the following conditions. Use the two- letter abbreviations for each stage: IF, RF, EX, M, WB a. Assume stalling for both control (branch) hazards and data hazards. For control hazards, IF of the dependent (later) instruction aligns with WB of the earlier instruction. For data hazards, RF of the dependent instruction must follow WB of the earlier instruction Cycle 0 1 2 3 45 6 7 8 9 10 11 12 13 14 15 16 17 18 19 22 21 22 w $t1, 0(Sa0) beq St1, S0, targ1 addi $a0, $a0, 4 add $t1, $t1, $t3 w $t1, 0(St1) add Svo, $vO, t1