Question: The following code is written in Verilog utilizing SPARC Architecture, please convert the code into MIPS Architecture: module ALU (output reg [31:0] ALU_Out, output reg
The following code is written in Verilog utilizing SPARC Architecture, please convert the code into MIPS Architecture:
module ALU (output reg [31:0] ALU_Out, output reg Negative, Zero, Overflow, Carry, input [31:0] A, B, input [5:0] Status, input c_in);
always @ (Status, A, B, c_in)
begin
case({Status[3], Status[2], Status[1], Status[0]})
// ARITHMETIC
// ADD, ADDcc
4'b0000:
begin
ALU_Out = A + B;
if(Status[4])
begin
Negative <= ALU_Out[31];
if(ALU_Out == 32'b00000000000000000000000000000000) Zero <= 1'b1;
else Zero <= 1'b0;
if((A[31] && B[31] && !ALU_Out[31])||(!A[31] && !B[31] && ALU_Out[31])) Overflow <= 1'b1;
else Overflow <= 1'b0;
if((A[31] && B[31]) || (!ALU_Out[31] && (A[31] || B[31]))) Carry <= 1'b1;
else Carry <= 1'b0;
end
end
// ADDX, ADDXcc
4'b1000:
begin
ALU_Out = A + B + c_in;
if(Status[4])
begin
Negative <= ALU_Out[31];
if(ALU_Out == 32'b00000000000000000000000000000000) Zero <= 1'b1;
else Zero <= 1'b0;
if((A[31] && B[31] && !ALU_Out[31])||(!A[31] && !B[31] && ALU_Out[31])) Overflow <= 1'b1;
else Overflow <= 1'b0;
if((A[31] && B[31]) || (!ALU_Out[31] && (A[31] || B[31]))) Carry <= 1'b1;
else Carry <= 1'b0;
end
end
// SUB, SUBcc
4'b0100:
begin
ALU_Out = A - B;
if(Status[4])
begin
Negative <= ALU_Out[31];
if( ALU_Out == 32'b00000000000000000000000000000000) Zero <= 1'b1;
else Zero <= 1'b0;
if((A[31] && !B[31] && !ALU_Out[31]) || (!A[31] && B[31] && ALU_Out[31])) Overflow <= 1'b1;
else Overflow <= 1'b0;
if((!A[31] && B[31]) || (ALU_Out[31] && (!A[31] || B[31]))) Carry <= 1'b1;
else Carry <= 1'b0;
end
end
// SUBX, SUBXcc
4'b1100:
begin
ALU_Out = A - B - c_in;
if(Status[4])
begin
Negative <= ALU_Out[31];
if( ALU_Out == 32'b00000000000000000000000000000000) Zero <= 1'b1;
else Zero <= 1'b0;
if((A[31] && !B[31] && !ALU_Out[31]) || (!A[31] && B[31] && ALU_Out[31])) Overflow <= 1'b1;
else Overflow <= 1'b0;
if((!A[31] && B[31]) || (ALU_Out[31] && (!A[31] || B[31]))) Carry <= 1'b1;
else Carry <= 1'b0;
end
end
//LOGICAL
//AND, ANDcc
4'b0001:
begin
ALU_Out = A & B;
if(Status[4])
begin
Negative <= ALU_Out[31];
if(ALU_Out == 32'b00000000000000000000000000000000) Zero <= 1'b1;
else Zero <= 1'b0;
Overflow <= 1'b0;
Carry <= 1'b0;
end
end
//ANDN, ANDNcc
4'b0101:
begin
if(!Status[5])
begin
ALU_Out = ~(A & B);
if(Status[4])
begin
Negative <= ALU_Out[31];
if(ALU_Out == 32'b00000000000000000000000000000000) Zero <= 1'b1;
else Zero <= 1'b0;
Overflow <= 1'b0;
Carry <= 1'b0;
end
end
else//SHIFT LEFT LOGICAL
begin
ALU_Out = A << B[4:0];
end
end
//OR, ORcc
4'b0010:
begin
ALU_Out = A | B;
if(Status[4])
begin
Negative <= ALU_Out[31];
if(ALU_Out == 32'b00000000000000000000000000000000) Zero <= 1'b1;
else Zero <= 1'b0;
Overflow <= 1'b0;
Carry <= 1'b0;
end
end
//ORN, ORNcc
4'b0110:
begin
if(!Status[5])
begin
ALU_Out = ~(A | B);
if(Status[4])
begin
Negative <= ALU_Out[31];
if(ALU_Out == 32'b00000000000000000000000000000000) Zero <= 1'b1;
else Zero <= 1'b0;
Overflow <= 1'b0;
Carry <= 1'b0;
end
end
else//Shift Right Logical
begin
ALU_Out = A >> B[4:0];
end
end
//XOR, XORcc
4'b0011:
begin
ALU_Out = A ^ B;
if(Status[4])
begin
Negative <= ALU_Out[31];
if(ALU_Out == 32'b00000000000000000000000000000000) Zero <= 1'b1;
else Zero <= 1'b0;
Overflow <= 1'b0;
Carry <= 1'b0;
end
end
//XORN, XORNcc
4'b0111:
begin
if(!Status[5])
begin
ALU_Out = ~(A ^ B);
if(Status[4])
begin
Negative <= ALU_Out[31];
if(ALU_Out == 32'b00000000000000000000000000000000) Zero <= 1'b1;
else Zero <= 1'b0;
Overflow <= 1'b0;
Carry <= 1'b0;
end
end
else//shift right arithmetic
begin
ALU_Out = $signed(A) >>> B[4:0];
end
end
endcase
end
endmodule
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