The following parameters are defined for a switching network: N=4= number of hops between two given end systems L=6000= message length in bits B= data rate, in bits per second (bps), on all links P=1080= fixed packet size, in bits H=80 = overhead (header) bits per packet S=0.2= call setup time (circuit switching or virtual circuit) in seconds T=0.02= call teardown time (circuit switching or virtual circuit) in seconds D=0.001= propagation delay per hop in seconds Given is a situation with the above parameters (including back to L =6000 ), but with a data rate of 9.3kbps (that is thousands of bits per second). Assume that there are no acknowledgment packets, but do not ignore teardown times. Ignore processing delay at the nodes. Compute the end-to-end delay to fully and properly complete virtual circuit packet switching. Use the scenario from Question 2, except there is a nonzero processing delay for both virtual circuit switching ( Tproc=Tv d and datagram switching (Tproc=Tdas ). Assume the processing delay for a virtual circuit switching at each node is TvC=. 1.1ms. (that is. milliseconds). Now compare with datagram packet switching. Find the minimum datagram processing time (Tdatt in milliseconds for which virtual circuit switching has a lower end-to-end delay than datagram packet switching. Use setup time =200ms. and teardown time =20ms. You must include both setup and teardown time. The following parameters are defined for a switching network: N=4= number of hops between two given end systems L=6000= message length in bits B= data rate, in bits per second (bps), on all links P=1080= fixed packet size, in bits H=80 = overhead (header) bits per packet S=0.2= call setup time (circuit switching or virtual circuit) in seconds T=0.02= call teardown time (circuit switching or virtual circuit) in seconds D=0.001= propagation delay per hop in seconds Given is a situation with the above parameters (including back to L =6000 ), but with a data rate of 9.3kbps (that is thousands of bits per second). Assume that there are no acknowledgment packets, but do not ignore teardown times. Ignore processing delay at the nodes. Compute the end-to-end delay to fully and properly complete virtual circuit packet switching. Use the scenario from Question 2, except there is a nonzero processing delay for both virtual circuit switching ( Tproc=Tv d and datagram switching (Tproc=Tdas ). Assume the processing delay for a virtual circuit switching at each node is TvC=. 1.1ms. (that is. milliseconds). Now compare with datagram packet switching. Find the minimum datagram processing time (Tdatt in milliseconds for which virtual circuit switching has a lower end-to-end delay than datagram packet switching. Use setup time =200ms. and teardown time =20ms. You must include both setup and teardown time