The following question based on memory system:

The diagram below shows a very small byte-addressable memory system consisting of two modules each of which is 32 bits wide. The memory is implemented using DRAM with an access time of 14ns 32-bit Address bus 32 36 40 0 4 12 16 20 24 28 48 52 56 60 32-bit Data bus dicate whether this is a high order interleaved or a low order interleaved memory system. b) (4) What is the time that would be required to read a 32-bit word from address 12? c) (4) What is the amount of time that would be required to read a 32-bit word from address 30