The following question should be written as verilog code. This assignment is being done in Vivado and aims to program an FPGA Board (ZyboZ7).

1. Program a 4-bit counter using LEDS 0,1,2, & 3 (don't use the switches). The count value should update approximately every 1 second. Use BTN0 and BTN1 as push buttons on the ZYBO Z7-10 board to control the direction of the count. For example, when BTN0 button is pressed, the counter should count up. Likewise when button BTN1 is pressed, the counter should count down. When neither button is pressed, the count should remain the same. You will need to make one verilog file, and one constraints file (.xdc).

Here is what I have so far, my bitstream is not generating, so there are errors within these 2 codebases.

"counter.v"

`timescale 1ns / 1ps

module counter(

input wire clk, input wire btn0, output wire [3:0] leds, input clock_in, output reg clock_out, reg[27:0] counter=28'd0 ); parameter DIVISOR = 28'd2; reg [26:0] count; always @(posedge clock_in) begin counter <= counter + 28'd1; if(counter>=(DIVISOR-1)) counter <= 28'd0; clock_out <= (counter

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"counter.xdc"

#the next 3 lines connect the clock port R17 to our clk input set_property PACKAGE_PIN K17 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add name sys_clk_pin -period 5.00 -waveform {0,4} [get_ports clk]

#BUTTON0 set_property PACKAGE_PIN K18 [get_ports {btn3}] set_property IOSTANDARD LVCMOS33 [get_ports {btn0}]

#LED0 set_property PACKAGE_PIN M14 [get_ports {leds[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {leds[0]}]

#LED1 set_property PACKAGE_PIN M15 [get_ports {leds[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {leds[1]}]

#LED2 set_property PACKAGE_PIN G14 [get_ports {leds[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {leds[2]}]

#LED3 set_property PACKAGE_PIN D18 [get_ports {leds[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {leds[3]}]