The following VHDL code contains erroneous syntax. Re- write the code in its corrected format onto your answer sheet assume that din is a 16-bit vector and that the ld, l and cl inputs are 1-bit wide. 1 process (clk) : signal reag std logie vector(1s donto o) 3 begin 4 i cl-'l' then reg(others:0) 6 elae ? clk#1, and clkevent then 7 if ld-1 9 eg din; end if: if lr-'1' then 10 down to 0) & "O. ; regreg (14 2 13 14 else zegeg(15 dowmto 1 rea