The Forwarding unit performs the following checks to detect MEM hazard in which the data is forwarded from the MEM/WB interstage buffer (precisely speaking, from the MUX controlled by the MemtoReg signal).

// Check for RegisterRs (Check for RegisterRt is similar)

if (MEM/WB.RegWrite

and (MEM/WB.RegisterRd != 0)

and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd !=0)) and (EX/MEM.RegisterRd != ID/EX.RegisterRs)

and (MEM/WB.RegisterRd = ID/EX.RegisterRs))

// condition #1

// condition #2

// condition #3 // (included in condition #3)

// condition #4

a) [6 points] Why should the Forwarding unit check condition #1? Be precise.

b) [6 points] Why should the Forwarding unit check condition #2? Be precise.

c) [6 points] Why should the Forwarding unit check condition #3? Be precise.

IF: Instruction fetch ID: Instruction decode and register read Ex: Execute/Address calc MEM: Memory Access WB: Write back 4 nstr (25:21 (koad-use) DVEX.RegisterRt EX Shift left 2 Branch MemtoReg MemWrite nstr [31:261 Instr [25:21) Read register 1 addresS Instr [20:16] data 1 Instr [31:0] register 2 ALU Write data 2 sters Data Sign- extend 16-32 Instr [15:0] ALU Instr [5:0] Instr [20:18] IM Instr [15:11 Forwarding IFID ID/EX EXIMEM MEM/NB IF: Instruction fetch ID: Instruction decode and register read Ex: Execute/Address calc MEM: Memory Access WB: Write back 4 nstr (25:21 (koad-use) DVEX.RegisterRt EX Shift left 2 Branch MemtoReg MemWrite nstr [31:261 Instr [25:21) Read register 1 addresS Instr [20:16] data 1 Instr [31:0] register 2 ALU Write data 2 sters Data Sign- extend 16-32 Instr [15:0] ALU Instr [5:0] Instr [20:18] IM Instr [15:11 Forwarding IFID ID/EX EXIMEM MEM/NB